1. Field of the Invention
The present invention relates to a semiconductor memory constituted of memory cells having complementary storage nodes.
2. Description of the Related Art
Along with miniaturization of the device structure of a semiconductor, an insulator film constituting a transistor has been going thinner. Accordingly, reliability of the transistor has been on the decrease. A power supply voltage supplied to a semiconductor integrated circuit has been lowering year by year in order to prevent the decrease in the reliability. When the power supply voltage lowers to be less different from a threshold voltage of the transistor, the transistor is not easily turned on. Accordingly, a write margin or a read margin of a memory cell has been reducing.
There is a proposed technique for improving the read margin of a memory cell in an SRAM by making larger a difference between a power supply voltage supplied to a memory cell and a ground voltage during a read operation than during a standby time (for example, disclosed in Japanese Unexamined Patent Application Publication No. Sho 58-211391). Also, there is another proposed technique for improving the write margin and the read margin of a memory cell by supplying a power supply voltage boosted in a booster to a memory cell during a standby time and stopping the supply of the power supply voltage to the memory cell during an access time to the memory cell (for example, disclosed in Japanese Unexamined Patent Application Publication No. Hei 9-51042). Specifically, a switch (pMOS transistor) that turns on during the standby time and turns off during the access time is provided between a power supply line and the memory cell.
The above-described two techniques, however, require an exclusive power supply line in addition to an ordinary power supply line and a ground line. It also requires a circuit generating a voltage supplied to the exclusive power supply line. This increases circuit scale of a semiconductor memory, leading to cost increase. Further, according to the above-described first technique, the increase in the difference between the power supply voltage supplied to the memory cell and the ground voltage may possibly lower reliability because a high voltage is applied to a transistor constituting the memory cell. The above-described second technique involves a possibility that data already held in the memory cell is lost due to the stop of the supply of the power supply voltage during the read access time to the memory cell. Besides, the switches that turns off during the access time have to be formed for word lines respectively, in order to prevent the loss of the data held in memory cells connected to unselected word lines.